1. Field of the Invention
The present invention relates to semiconductor devices, and particularly to a semiconductor device that transfers data using complementary data buses.
2. Description of the Background Art
A synchronous dynamic random access memory of a double data rate (DDR-SDRAM) is conventionally known as an example of a synchronous type semiconductor memory device. This semiconductor memory device reads out data in units of one column block each. More specifically, data of two bits (called even-numbered address data and odd-numbered address data) is read out by accessing the region whose least significant bit CA0 of the column address is 0 (region of an even-numbered address) and the region whose least significant bit CA0 of the column address is 1 (region of an odd-numbered address) at the same time.
These semiconductor memory devices employ the complementary data bus structure as the bus to transfer the data read out for the purpose of reducing power consumption and improving the speed.
A conventional semiconductor memory device will be described with reference to FIG. 8. Referring to FIG. 8, a semiconductor memory device 9000 includes a pair of complementary data buses DB, DB#, a memory cell array 900, a row related control circuit 901 performing a row select operation of memory cell array 900, a column related control circuit 902 performing a column select operation of memory cell array 900, a driver unit 903, a clock buffer 904 receiving external clocks extCLK and extCLK# complementary to each other, and an internal clock signal generation circuit (DLL: Delayed Locked Loop) 905 receiving the output of clock buffer 904 to generate an internal clock.
Memory cell array 900 includes a plurality of memory cells arranged in a matrix, a plurality of word lines arranged corresponding to a plurality of rows, and a plurality of bit lines arranged corresponding to a plurality of columns. Memory cell array 900 is divided into a block B0 of an even-numbered address, and a block B1 of an odd-numbered address. In the drawing, a word line WL, bit lines BL00, BL01, a memory cell M0 of block B0 connected to word line WL, and a memory cell M1 of block B1 connected to word line WL are depicted representatively. Even-numbered address data Even designates data read out from block B0 whereas odd-numbered address data Odd designates data read out from block B1.
Row related control circuit 901 renders a corresponding word line active according to an address signal. Column related control circuit 902 outputs the data on the selected bit line (readout data) according to an address signal.
Driver unit 903 receives readout data output from column related control circuit 902 to provide the readout data and data that is complementary to the readout data to data buses DB and DB#, respectively.
Semiconductor memory device 9000 further includes a receiver 906 to receive even-numbered address data Even from complementary data bus pair DB, DB#, a receiver 907 receiving odd-numbered address data Odd from complementary data bus pair DB, DB#, an output register 908 receiving and providing to a data input/output terminal DQ the output of receiver 906 according to an internal clock signal intCLKD output from internal clock signal generation circuit 905, and an output register 909 receiving and providing to data input/output terminal DQ the output of receiver 907 according to an inverted signal of internal clock signal intCLKD.
The relationship between complementary data bus pair DB, DB# and the receivers of conventional semiconductor memory device 9000 will be described here with reference to FIG. 9.
An equalize circuit T to equalize data buses DB and DB# is located between data bus DB and data bus DB#. In FIG. 9, a transistor T connected between data bus DB and data bus DB# is depicted as an example of equalize circuit T.
Transistor T receives an equalize signal EQ at its gate. An equalize operation is executed when equalize signal EQ attains an H level, whereby data buses DB and DB# are electrically connected.
Receiver 906 includes an amplifier 910 for the even-numbered address. Amplifier 910 responds to an amplifier activation signal SE of an activated state to amplify the potential difference between data buses DB and DB# for output.
Receiver 907 includes an amplifier 911 for the odd-numbered address. Amplifier 911 responds to amplifier activation signal SE of an active state to amplify the potential difference between data buses DB and DB# for output.
Amplifier activation signal SE is opposite in phase to equalize signal EQ, and is rendered active during the period an equalize operation is suppressed.
A readout operation of semiconductor memory device 9000 will be described with reference to FIG. 10. Equalize signal EQ is at an H level (active state). Data buses DB and DB# are equalized by the equalize circuit.
Even-numbered address data Even and odd-numbered address data Odd that are the subject of readout are selected. Then, equalize signal EQ is driven to an L level. First, even-numbered address data Even is transmitted onto complementary data bus pair DB, DB#. Amplifier activation signal SE attains an H level, whereby the potential difference between data buses DB and DB# is amplified in amplifier 910.
For the subsequent data transfer, equalize signal EQ is driven to an H level. The pair of complementary data buses DB, DB# are equalized.
Then, equalize signal EQ is pulled down to an L level. Odd-numbered address data Odd is transmitted onto complementary data bus pair DB, DB#. Amplifier activation signal SE is driven to an H level, whereby the potential difference between data buses DB and DB# is amplified in amplifier 911.
For the subsequent read/write operation, equalize signal EQ is driven to an H level again.
According to the above-described structure of conventional semiconductor memory device 9000, the complementary data bus pair must always be equalized after data is output to the complementary data bus pair in reading out data continuously.
Therefore, the time for equalization cannot be reduced. More specifically, there was a problem that the chip could not be operated at 143 MHz or above.
An approach can be considered to provide a complementary data bus pair corresponding to respective even-numbered address data and odd-numbered address data to solve this problem. However, the chip size will be increased with the above-described structure.
Furthermore, it is difficult to obtain data of sufficient amplitude at the reception side (receiver side) as the chip size is increased and the data bus becomes longer. This reduction in data amplitude prevents high speed operation.
In view of the foregoing, an object of the present invention is to provide a semiconductor device that can transfer data speedily and reliably.
According to an aspect of the present invention, a semiconductor device includes a memory cell array with a plurality of memory cells, a data bus pair of a first data bus and a second data bus transmitting data complementary to each other, a read circuit reading out n (n is an integer of at least 2) storage data out of a plurality of storage data stored in a plurality of memory cells and providing n storage data continuously to the data bus pair in a data readout operation, a plurality of output circuits provided corresponding to n storage data, respectively, each sensing potential difference between the first and second data buses to amplify the sensed potential difference for output, and a data transfer processing circuit arranged between the data bus pair and the plurality of output circuits for the plurality of output circuits to continuously receive corresponding storage data alternately.
Preferably, each of the plurality of output circuits includes a circuit amplifying the potential difference between a first node whose voltage level changes according to the potential of the first data bus and a second node whose voltage level changes according to the potential of the second data bus. The data transfer processing circuit includes a plurality of first capacitive elements arranged corresponding to the plurality of output circuits, respectively, each connected between the first data bus and a corresponding first node, a plurality of second capacitive elements arranged corresponding to the plurality of outputs circuits, respectively, each connected between the second data bus and a corresponding second node, and a plurality of equalize circuits provided corresponding to the plurality of output circuits, respectively, each connected between a corresponding first node and a corresponding second node. The plurality of equalize circuits equalize the corresponding first node and the corresponding second node continuously and alternately.
Further preferably, the equalize operation of a corresponding equalize circuit is suppressed when one of the plurality of output circuits performs differential amplification.
According to the above semiconductor device, an equalize period is not required between each data transfer when data is transferred continuously using a pair of complementary data buses. Therefore, data can be transferred at high speed.
By coupling the amplifier and the complementary data bus pair through a capacitor, the amplitude of the data on the data bus can be sensed to read the actual data. Therefore, storage data can be output reliably and continuously even when the data bus becomes longer.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.